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Request evaluation samplesEP1S10F484C7N Embedded - FPGAs (Field Programmable Gate Array) by Intel
EP1S10F484C7N is a Embedded - FPGAs (Field Programmable Gate Array) model from Intel, presented on TrustCompo for buyers who need clear sourcing and review context before RFQ. This listing sits in the Integrated Circuits (ICs) / Embedded - FPGAs (Field Programmable Gate Array) product path. IC FPGA 335 I/O 484FBGA. TrustCompo combines the available model, brand, hierarchy, and specification details around EP1S10F484C7N so buyers can move faster from review to quotation.
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Key specifications
Series
Stratix®
Min Quantity
1
Category
Integrated Circuits (ICs)Sub Category
Embedded - FPGAs (Field Programmable Gate Array)Description
IC FPGA 335 I/O 484FBGA
key Attributes
-
Datasheet
View EP1S10F484C7N DatasheetTechnical document
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Globally recognized certifications
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ISO 9001
Quality management processes for more consistent sourcing and handling.
AS9120B
Aerospace-focused distribution controls for traceability and reliability.
ISO 14001
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ESD Control
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Product overview
Overview
This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.
Features Configuration devices for SRAM-based LUT devices offer the following features:
• Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
• Easy-to-use four-pin interface
• Low current during configuration and near-zero standby mode current
• Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
• Available in compact plastic packages
• 8-pin plastic dual in-line (PDIP) package
• 20-pin plastic J-lead chip carrier (PLCC) package
• 32-pin plastic thin quad flat pack (TQFP) package
• EPC2 device has reprogrammable flash configuration memory
• 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface
• Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
• Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
• Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
• nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration
Features Configuration devices for SRAM-based LUT devices offer the following features:
• Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
• Easy-to-use four-pin interface
• Low current during configuration and near-zero standby mode current
• Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
• Available in compact plastic packages
• 8-pin plastic dual in-line (PDIP) package
• 20-pin plastic J-lead chip carrier (PLCC) package
• 32-pin plastic thin quad flat pack (TQFP) package
• EPC2 device has reprogrammable flash configuration memory
• 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface
• Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
• Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
• Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
• nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration
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Popular Specs Surfaced First
Product Attribute
Part Status
Active
Product Attribute
REACH Status
REACH Unaffected
Product Attribute
Lead Free
Lead Free
Product Attribute
Packaging
Bulk
Product Attribute
Published
2006
Product Attribute
Factory Lead Time
8 Weeks
Part Status
Active
REACH Status
REACH Unaffected
Lead Free
Lead Free
Packaging
Bulk
Published
2006
Factory Lead Time
8 Weeks
Termination
SMD/SMT
Max Operating Temperature
85°C
Categories
Integrated Circuits (ICs)
Peak Reflow Temperature (Cel)
260
Technology
CMOS
Terminal Form
BALL
HTS Code
8542.39.00.01
Width
23mm
Number Of Pins
484
Radiation Hardening
No
Reflow Temperature-Max (S)
40
Mount
Surface Mount
Pbfree Code
yes
Terminal Position
BOTTOM
Min Operating Temperature
0°C
Terminal Pitch
1mm
Supply Voltage
1.5V
Number Of Terminations
484
Pin Count
484
Length
23mm
Package / Case
FBGA
Operating Supply Voltage
1.5V
Operating Supply Current
37mA
Sub-Categories
Embedded - FPGAs (Field Programmable Gate Array)
Subcategory
Field Programmable Gate Arrays
Manufacturer
Intel
ECCN
3A991D
Temperature Grade
COMMERCIAL EXTENDED
Series
Stratix®
Min Supply Voltage
1.425V
Max Supply Voltage
1.575V
Number Of Outputs
426
Organization
1200 CLBS
Number Of I/O
335
Frequency
420.17MHz
Manufacturer'S Part No.
EP1S10F484C7N
Terminal Finish
Tin/Silver/Copper (Sn/Ag/Cu)
Programmable Logic Type
FIELD PROGRAMMABLE GATE ARRAY
Power Supplies
1.51.5/3.3V
RAM Size
112.4kB
Number Of Logic Elements/Cells
10570
Frequency (Max)
66MHz
Number Of Logic Blocks (LABs)
1057
Number Of CLBs
1200
Memory Size
112.4kB
Height Seated (Max)
3.5mm
RoHS Status
RoHS Compliant
REACH SVHC
Unknown
HTSUS
8542.39.0001
Moisture Sensitivity Level (MSL)
3 (168 Hours)
JESD-609 Code
e1
ECCN Code
3A991
Common questions
Product FAQ
Quick answers for buyers reviewing EP1S10F484C7N, stock, documentation, and sourcing steps.
What is EP1S10F484C7N?
EP1S10F484C7N is a Embedded - FPGAs (Field Programmable Gate Array) component from Intel. This product page summarizes the core sourcing details buyers need before checking price, availability, documentation, or samples.
What package and description are listed for EP1S10F484C7N?
EP1S10F484C7N is listed with package reference -. The current product description is IC FPGA 335 I/O 484FBGA, and buyers should confirm package, footprint, and electrical details against the datasheet or quotation notes before approval.
Is EP1S10F484C7N available in stock?
This page currently shows 44337 units in stock and 29444 units available for EP1S10F484C7N. Because electronic component availability can change quickly, submit an RFQ to confirm live stock, lead time, and final pricing.
Can I request a quote or sample for EP1S10F484C7N?
Yes. Use the Quick Quote or Request Sample action on this page to send the quantity and sourcing requirements for EP1S10F484C7N by Intel. The TrustCompo team can review price, availability, and documentation support.
Is a datasheet available for EP1S10F484C7N?
Yes. This page links to the datasheet for EP1S10F484C7N by Intel, so engineers and buyers can review package, ratings, and application details before purchase.
How should buyers verify EP1S10F484C7N before ordering?
Buyers should confirm the manufacturer, package, quantity, target price, RoHS or compliance needs, and any Certificate of Conformance or traceability requirements for EP1S10F484C7N before approving the order.
Embedded - FPGAs (Field Programmable Gate Array)
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